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sh65 11/sh6 5 1 1 b 16k 4-b i t m i crocontro lle r with lcd driver 1/22 ver 2.2 f eat u r es ? sh 6610-b a se d s i ng le-c hip 4-bi t m i croco n trol ler w i th lc d driv er ? r o m : 16 k 16 bit s (ba nk sw itche d) ? r a m : 512 4 bit s (sys t em co ntrol reg i st er & da ta mem o r y ) ? o peratin g vol t age rang e: 2. 4v - 5. 5v ? 8 cm o s i/o ports ? 4 lev el sub r out ine nes tin g in clu din g i nterru pts` ? o ne 8-bi t ti mer w i th pr e-div i d e r c i rc uit ? w a r m -u p ti m e r f o r p o w e r-on res e t ? pow e rful inte rrupt so urce s: -t imer0 in terru pt -port b in terrup t (fa lli ng e dge) ? sy stem clo ck: 2 m h z single-p i n v olt age-c on t rol l ed osc ill ator ? t able bran ch a nd r et urn c o nst ant i nstr uct ion s for t able d a ta g e nerat ion ? data po inter w i th spe c i a l sy stem reg i st er c ontro l ? tw o low pow er operating mo des - h a lt and st o p ? instr u cti on cy cle tim e : 2 s for 2 m h z v o ltage- contr o ll ed o s c ill ator ? built-i n 2- cha nne l psg for soun d ef fect s, sw itch ab le t o nois e c han nel ? d i r e ct ly dr iv es spe a ker ? t y pe b lc d driv e cir c uit ? lc d driv er: 4 0 8 (1 /8 duty cy c l e, 1/4 b i a s ) ? lc d off by pro g ra mmi ng lc d o ff regi ster ? av ailabl e i n ch i p fo r m g e n e ral des c rip t io n sh 6511/sh 6 511b is a s i ng le c h ip 4 b i t c dedic ate d ch ip f or ha ndh eld ga mes . t his d ev i ce int egrat es a sh 661 0 4-bit c p u core w i th r a m , ro m , timer, 2-c han nel psg , and dot matr ix lc d driv er. p a d configura t ion 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 seg23 seg21 seg22 seg24 seg25 seg26 seg27 seg28 seg29 seg30 seg31 seg32 seg33 seg34 seg36 seg35 sh6511/ SH6511B 27 26 25 24 23 22 18 17 16 com4 com5 com6 com7 com8 seg1 21 20 19 seg2 com3 seg7 6 5 4 3 2 11 2 11 10 9 8 7 15 14 13 31 30 29 28 46 45 44 43 40 37 36 35 34 33 32 38 39 41 42 48 47 seg38 seg37 seg6 seg5 seg4 seg3 com2 com1 pb3 pb2 pb1 s e g 3 9 s e g 4 0 t e s t r e s e t a o u t o p 0 o s c i o p 1 p a 0 p a 1 p a 2 p a 3 p b 0 g n d v d d s e g 9 s e g 8 s e g 1 0 s e g 1 1 s e s 1 2 s e g 1 3 s e g 1 4 s e g 1 5 s e g 1 6 s e g 1 7 s e g 1 8 s e g 1 9 s e g 2 0 http://
sh6511/SH6511B 2/22 ver 2.2 blo ck di ag ra m segment driver lcd ram 2-channel psg timer0 misc. ckt. 16k x 16 rom cpu lcd voltage i/o port common driver ram seg1 - 40 com1 - 8 reset test osci aout porta portb p a d d e s c r i ption pad n o. s y m bol i/o shar ed b y r eset d e scr i ption 1 - 21, 46 - 64 seg 1 - 40 o s egme n t s i gn al outp ut for lc d di sp lay 22 - 2 9 c o m 8 -1 o c ommo n s i gn al o u tp ut for lc d di spl a y 30 - 3 3 pb3 - pb0 i/o po rt in t . 0fh b it pro g ram m ab le i / o , vect or in terrup t 34 - 3 7 pa3 - pa0 o 0 output p o rts 38, 41 o p 1, o p 0 i bonding option 39 v dd power supply 40 o s c i i osc input 42 g n d g round 43 ao u t o audio output 44 reset i reset input (active low) 45 te st i test ( no connect for user)
sh6511/SH6511B 3/22 ver 2.2 func tiona l de s c r i ption 1. c p u t he c p u core c ont ain s th e fo llow i ng f unct i on bl oc ks: program c ount er, alu , c a rry flag , ac cu mula tor, t abl e bra n c h re g i s t e r (t br), da ta po i n te r (inx , dph, dpm a n d d p l), and s t ac k. (a) pc (progra m co unter) t he pc is u s ed for r o m address i ng co nsi s ti ng o f 12-b i t s : page r e g i st er (pc 11) , and r i pple ca rry count er (pc 10 - pc0). t he progra m c ount er nor ma lly in crea se s by on e (+1) w i th each ex ecutio n of an i n str u ct ion ex cept in t he f o ll ow ing cas e s: 1) w h e n ex ecuting a ju mp in struc t io n (s uch as jm p, ba0, bac); 2) w h e n ex ecuting a s ubro u tin e c a ll in stru ctio n (c all); 3) w h e n an i n terru pt o c c u rs; 4) w h e n t he c h i p i s at init ial reset . t he progr am coun ter i s l oad ed w i th da ta c o rre spo ndin g to ea ch instr u ct ion. t he un cond iti onal ju mp ins t ruc t ion (jm p ) can be s e t a t 1-b i t p age r egi ster for h i gh er tha n 2k. program c ount er c an o n ly ad dres s a 4k pr ogram r o m . t o addre ss 16k pr ogra m ro m , use ban k sw itch (r efe r to t he r o m descrip tio n in s ect ion 3 for det ail s ). (b) alu an d cy alu perfor m s arit hme t ic and lo gic ope rati ons. t he alu prov ide s th e fo llow i ng f unc tio n s: binary add iti on/ subtr act ion (adc, sbc, add, sub, adi, sbi) d e ci mal adj ust m ent for addi tion /s ubtra cti on (d aa, d as) logi c op erat ion s (an d , eo r , o r , an d i, eo r i, o r i) dec i s i on (ba0, ba1 , ba2, ba3 , baz, bac) t he c a rry flag (c y ) hold s th e ari t hm eti c op erat ion a l u ov erflow . d u ring interr upt or c a ll in stru ctio n, c a rry is pus hed ont o stac k a nd re stor ed fr om sta ck by r t n i. it i s u naff ect ed by an r t n w i n str u ct ion. (c ) ac c u m u la tor accu mul a tor is a 4-b i t re gi ster h o ld ing the r e su lts of t h e arith m eti c l ogi c u n it. in conj unc tio n w i th alu , d a ta tr ans fers betw een the ac cu mul ator a nd sy ste m reg i st er, lc d r a m , or dat a me mory c an be p e rform ed. (d) stac k a group of re gi ster s us ed t o s a v e the co ntent s o f cy & pc (10-0) seq uent ial l y wi th each su brout ine ca ll or int e rrup t. it is or gan iz ed 13 bit s 4 lev e ls. t h e m sb is s a v ed for c y . 4 lev e ls are t he max i mum all o w ed for s ubrou tin e c a ll s an d interru pts . t he conte n ts of st ac k are r e tur ned seq uent ial l y to th e pc w i th the retur n i n str u ct ion s (rt n i/rt n w ) . st ac k i s operat ed o n a f i rst- in, la st-out ba si s. t his 4-lev e l ne sti ng incl ude s b o th subr outi ne cal l s a n d inter r upt r e qu est s . n o t e that pr ogra m ex ecuti on may ent er an abn orm a l state if t h e numb er of ca lls an d int errup t req ues ts ex ceeds 4, an d the botto m of sta c k w ill be shi fted out.
sh6511/SH6511B 4/22 ver 2.2 2. r a m r a m consi s t s of gen eral- purpo se data me mory , lc d r a m , and sy st em r egi ster s. (a) r a m addressi ng d a ta m e mory a nd sy ste m reg i st er c an b e a cce ss ed i n on e instr u ct ion by dire ct a ddre s s i ng. fol l ow ing i s th e m e mory allo cat ion map : $000 - $01 f: sy ste m re gis t er a nd i/o (3 2 4 bi ts) $020 - $1ff : da ta m e mory (48 0 4 bit s ) $200 - $2ff : re s e rv ed $300 - $34 f: lc d ra m space (80 4 b i ts) (b) data m e m o ry d a ta m e mory i s or gan iz ed a s 48 0 4 bit s ($ 020 - $1f f). becau s e of it s stati c n ature , the r a m can ke ep d ata a fter the c p u ent ers st o p or h a lt . (c ) sy s t e m reg i s t ers t he conf igura t io n of sy ste m reg i st ers is as fol l ow s: bit 3 b it 2 b it 1 b it 0 r/w r emarks $00 - i et 0 - iep r / w i nterru pt en able flags $01 - i r q t 0 - i r q p r / w i nterru pt req u e st flags $02 - t m 0 .2 tm 0.1 t m 0 .0 r / w t imer0 m ode r egi ster (t m0) $03 - - - - - r eserv e d $04 t l .3 t l .2 t l .1 t l .0 r / w t imer0 lo ad/ cou n ter register low digit $05 t h .3 t h .2 t h .1 t h .0 r / w t imer0 lo ad/ cou n ter register high digit $06 - - - - - r eserv e d $07 - - - - - r eserv e d $08 pa.3 pa.2 pa.1 pa.0 r / w port a $09 pb.3 pb.2 pb.1 pb.0 r / w port b $0a - - - - - - $0b - - - - - - $0c - - o p 1 o p0 r b ondi ng o p ti on $0d - - - - - r eserv e d $0e t b r .3 t br .2 t b r .1 t br.0 r / w t able bran ch r e gis ter (t br) $0f in x . 3 i n x .2 in x . 1 i n x .0 r / w p seud o in dex r egister ( i nx)
sh6511/SH6511B 5/22 ver 2.2 (c) sy ste m r e g i st ers ( c ont inue d) bit 3 b it 2 b it 1 b it 0 r/w r emarks $10 d p l.3 d pl.2 d p l.1 d pl.0 r / w data pointer for inx low nibble $11 - d p m .2 d p m . 1 d p m .0 r / w data pointer for inx middle nibble $12 - d ph .2 d p h . 1 d ph .0 r / w data pointer for inx high nibble $13 c 1 .3 c 1 .2 c 1 .1 c 1 .0 w psg channel 1 low digit $14 c 1 m c 1.6 c 1.5 c 1.4 w psg channel 1 high digit $15 c 2 .3 c 2 .2 c 2 .1 c 2 .0 w psg channel 2 low digit $16 c 2 .7 c 2 .6 c 2 .5 c 2 .4 w psg channel 2 $17 c 2 .11 c 2.10. c 2 .9 c 2 .8 w psg channel 2 $18 c 2 m c 2.14 c 2 .13 c 2.12 w psg channel 2 high digit $19 vo l1 vo l0 c h 2 en c h 1 en w b it 0: psg c h a nne l 1 enab le bit 1: psg c h a nne l 2 enab le bit 2, bit 3: volume control (initially 0, no sound) $1a - - p1.1 p1.0 w psg 1 prescaler $1b - - p2.1 p2.0 w psg 2 prescaler $ 1 c - t m. 2 t m. 1 lcdoff w b it 0: lc d pow e r c ontrol bit 2, bit 1: reserved for test mode (tmr) $1d - - - - - reserved for ice $1e - - - - - reserved for ice $1f - b n k 2 b n k 1 b n k 0 w bank register for rom (bnk), bit 3 reserved for ice (d) data p o int e r d a ta m e mory can be i ndir e ct ly addr es sed by the d a t a pointer . poi n ter addre s s is lo cate d i n reg i st er d p m (3-bit s) an d d p l (4- b it s). t he a ddre s s i ng r ang e c an h a v e 128 l oca tio ns. p s eu do index addre ss ( i n x ) is us ed t o rea d or write d a ta mem o ry , the n r a m address bit 9 -bit 0 c o me s from d p h , d p m and d p l. 3. r o m sh 6511/sh 6 511b can addr ess up to 16k 16 b i ts of progra m ar ea fro m $ 000 to $ 3 fff. ro m space in the s y s t em is 1 6 3 84 16 bit s . (a) vect or addr es s are a ($0 00 to $0 04) t he progra m i s s equ enti a lly ex ecute d . an area from addre ss $00 0 thro ugh $00 4 i s re serv ed f o r s pec ial int e rrupt serv ice rout ine s a s s t arti ng ex ecut ion of a v e ctor addre s s . addres s i nstru c ti on r e mark s $000 jm p j um p to reset $001 - r eserv ed $002 jm p j um p to t i m e r 0 $003 - r e serv ed $004 jm p j um p to pb (port b) * j m p can be re pla c ed by any ot her i n str u ct ion. (b) t able d a t a re fer e n c e t able d ata can be stor ed i n pro gra m m emory a nd can be referen c ed by us ing t a b l e bran ch (t jm p) and r e turn c onsta nt (r t n w ) ins t ruc t ion s . t he t a bl e bran ch r e gi ster (t br ) and accu mu lator (a) i s pl ace d by an off s et addr es s in pro gra m r o m . t j m p instruc t io n bra nch int o ad dre s s ((pc11 - pc8) ( 2 8 ) + (t br , a)). t he addre ss is deter min ed by r t n w t o retu rn l ook-u p v a l ue i n to (t br , a). r o m code bit 7 -bi t 4 i s p l a c ed into t b r an d bit 3 -bi t 0 i n to a.
sh6511/SH6511B 6/22 ver 2.2 (c) ban k sw itch m appin g progra m coun ter (pc 1 1 - pc 0) can only a ddress 4k r o m space. ba nk sw itch t e ch niq ue i s u s ed to ex tend t h e c p u ad dres s spa c e. t he l o w e r 2k of t he c p u ad dres si ng spa c e map s to low e r 2k of r o m spac e (ban k0). t he u pper 2k of the c p u addre s s i ng spa c e map s t o on e of t he sev en ban ks (ban k 1, 2, 3, 4, 5, 6, 7) of th e up per 1 4 k of r o m . (accor d in g to the b ank r egist er) t he bank sw itch map p in g i s as fol low s: cpu a ddress r o m space, bnk = 0 r o m space, bnk = 1 r o m space, bnk = 2 r o m space, bnk = 3 r o m space, bnk = 4 r o m space, bnk = 5 r o m space, bnk = 6 000-7f f 0000 - 07ff (bank 0) 0000 - 07ff (bank 0) 0000 - 07ff (bank 0) 0000 - 07ff (bank 0) 0000 - 07ff (bank 0) 0000 - 07ff (bank 0) 0000 - 07ff (bank 0) 800 - f ff 0800- 0fff (bank 1) 1000 -17ff (bank 2) 1800 -1fff (bank 3) 2000 -27ff (bank 4) 2800 -2fff (bank 5) 3000 -37ff (bank 6) 3800 -3fff (bank 7) system r e gis t er 0c h bit 3 b it 2 b it 1 b it 0 r /w remarks p o w er-on $0c - - o p 1 o p0 r bit0: bo ndi ng o p tio n 0, int e rna l w eak driv e bit1: bo ndi ng o p tio n 1, int e rna l w eak driv e pull h i gh pull l o w xx 0 1 y e s x x 0 0 op0 bond to gnd xx 1 1 o p1 bond to v dd xx 1 0 o p0 bond to gnd and op1 bond to v dd op0 gnd pcb sh6511/SH6511B bonding option pcb op0 = 0 op1 = 1 op1 vdd op0 gnd op1 vdd op0 gnd op1 vdd op0 gnd op1 vdd op0 = 0 op1 = 0 op0 = 1 op1 = 1 op0 = 1 op1 = 0 u p to 4 diff erent bon din g op tion s ar e po ss ibl e for the us er' s ne ed s. t he c hip' s progr am h a s 4 d i ffer ent progr am f l ow s that w ill v a ry depend ing on w h ich bondin g op tion is us ed. t he r eada b le co nten ts of o p 1 and o p 0 w ill d i ffer dep end ing on bo nd ing.
sh6511/SH6511B 7/22 ver 2.2 4. tim e r sh 6511/sh 6 511b has one 8-b i t ti mer f o r c ount -up, con s is tin g of an 8- bit cou n ter and a n 8-b i t pre-l oad ed regis t er. pre-scaler sync tosc 8-bit counter t0m f osc /4 t i mer prov id es t he f oll ow ing fun c ti ons: * program ma ble interv a l ti mer * read c ount er v a lu e (a) t i mer0 c o nfi gurat ion and o p erat ion: t i mer-0 i s an 8-b i t w r ite-only t i mer lo ad re gis t er (t l0l, t l0h ), and an 8- bit r ead-o n ly ti mer cou n ter (t c 0l, t c 0h ). each low order dig i ts and hi gh or der d i git s . t i m e r coun ter i s i n it ial i z ed by w r iting d a ta into the tim e r l oad regis t er (t l0l, t l0h ). first w r ite t he l o w - order di git, then the hig h -ord er di git. t i mer co unter is aut oma t ic ally l oad ed w i th th e co nte n ts of the l oade d reg i st er w hen th e hi gh or der dig i t i s w r itten or coun t ov erfl ow s occ urs. t i mer ov erf l ow w ill resul t in a interru pt i f the int e rrupt en able fla g i s s e t. t i mer ca n be progr am med in sev e ra l di ffere nt c l o c k sour ces by set t in g t i mer m ode r e g i st er (tm 0 ). (b) ti mer m ode r egi ster: t i mer m ode r egis t ers (tm 0 ) are 4-bi t reg i st ers use d for timer co ntrol as sh ow n in t able 1. m ode r egi ster sel e ct s input pul se so urce s to the tim er. table 1. tim e r0 mode r e gisters ($0 2 ) tm 0.2 tm 0 .1 tm 0.0 pres c a ler di vi d e ra ti o cl o c k so u r c e 00 0 /2 11 s y stem clo c k 00 1 /2 9 s y stem clo c k 01 0 /2 7 s y stem clo c k 01 1 /2 5 s y stem clo c k 10 0 /2 3 s y stem clo c k 10 1 /2 2 s y stem clo c k 11 0 /2 1 s y stem clo c k 11 1 /2 0 s y stem clo c k
sh6511/SH6511B 8/22 ver 2.2 5. i/o ports (a) fun c ti ona l des c rip t io n - c m o s ty pe output p o rt - p m o s as pull - up f o r in put on portb - o utput l o w initia lly for p o rta - o utput h i gh ini t ia lly for por t b - o perate s sa me as data me mory for arit hme t ic and lo gic in stru ctio ns (b) c i rcui t d i agr am s (po r t a and po r t b) a b c d bus latch r q v dd reset porta a b c d bus latch s q v dd weak driving, pull-up resistor - 100k ? reset portb (c) progr am min g - i/o port s ca n b e ac ce ss ed w i th th e rea d /w rite sy ste m re gi ster. - m emory -mapped addr es se s are li sted as fol l ow s: a ddress bit 3 b it 2 b it 1 b it 0 r /w remarks $08 pa.3 pa.2 pa.1 pa.0 r /w porta $09 pb.3 pb.2 pb.1 pb.0 r /w portb $0a - - - - - r eserved $0b - - - - - r eserved $0c - - o p 1 o p0 r o ptional register - u s ers ca n out put any v a lue to a n y i/o port bit at any t i me . - before r eading portb i/o bits, the user needs to output "1" to the same bit.
sh6511/SH6511B 9/22 ver 2.2 6. programm a ble sound g e n e rator (psg ) 2-c hann el psg i s pr ov ided. c han nel 1 i s a 7-bit ps eud o ran dom co unter . c han nel 2 i s a 15-bit p s eu do ra ndo m coun ter. m ode bits c h 1m , c h 2m determine w hich of ea ch p s e udo ra nd om cou nter w ill be a noi se or a t one gen erator . t o redu ce p o w er con s um pti on, d i s able the so und effe ct g ener ator d u rin g bo th st o p and h a lt . note : d on?t ena ble tw o psg chann el s tog e th er to prod uce one ton e , or it w ill pr odu ce som e u npred ict ed e rrors. if it i s nece s s ary to u s e 2 ch ann els tog ether (ex . t o play tw o channe l m elo dy ), don ?t l et th e s c or e alw ay s be the sa me to ne s a s w e can do, t hen t he unpre d i c ted error s w ill no t o ccur or it w ill be ign o re t h roug h u s er h eari n g c hanne l 2 t o n e mode is sa me as c h anne l 1 . (7-b it p s eu do-ra ndo m c ount er). t his el imi nate s som e pr ogra m m i ng cod es. a ddress bit 3 b it 2 b it 1 b it 0 r /w remarks $13 c 1 .3 c 1 .2 c 1 .1 c 1 .0 w psg c hannel 1 low digit $14 c 1 m c 1.6 c 1.5 c 1.4 w psg c hannel 1 h i gh digit $15 c 2 .3 c 2 .2 c 2 .1 c 2 .0 w psg c hannel 2 low digit $16 c 2 .7 c 2 .6 c 2 .5 c 2 .4 w psg channel 2 $17 c 2 .11 c 2.10. c 2 .9 c 2 .8 w psg channel 2 $18 c 2 m c 2.14 c 2 .13 c 2.12 w psg c hannel 2 h i gh dig i t $19 vo l1 vo l0 c h 2 en c h 1 en w b it 0: psg c h a nne l 1 enab le bit 1: psg c h a nne l 2 enab le bit 2, b i t 3: v o lu me control (initially 0, no sound) $1a - - p1.1 p1.0 w psg 1 pres caler $1b - - p2.1 p2.0 w psg 2 pres c a ler p.1 p .0 pr escaler d i v i de r a tio c lock sour c e actual clock 0 0 1 32 kh z 32 khz 0 1 2 32 khz 16 khz 1 0 4 32 khz 8 khz 1 1 8 32 khz 4 khz music tabl e1: follow i ng is the mu sic s c al e refer e n c e ta ble for cha nne l 1 (or ch ann el 2) und er ac tual c l o ck= 32kh z . note ideal freq. n lsfr (c 1.6~c 1 .0) (c 2.14~c 2 . 8 ) r eal freq. error % n ote ideal freq. n lsfr (c 1.6~c 1 .0) (c 2.14~c 2 . 8 ) r eal freq. error % c3 130.8 1 122 20 131.1 5 0.26% g4 392.0 4 1 5 8 390.24 -0.44% d3 146.8 3 109 51 146.7 9 -0.03% a4 440.0 3 6 1 a 444.44 1.01% e3 164.8 1 97 45 164.9 5 0.08% b4 493.9 3 2 2 5 500.00 1.24% f3 174.6 1 92 33 173.9 1 -0.40% c5 523.2 3 1 4 b 516.13 -1.36% g3 195.9 9 82 27 195.1 2 -0.44% d5 587.3 2 7 3 b 592.59 0.90% a3 220.0 0 73 21 219.1 8 -0.37% e5 659.2 2 4 5 c 666.67 1.13% b3 246.9 4 65 44 246.1 5 -0.32% f5 698.4 2 3 3 9 695.65 -0.40% c4 261.6 2 61 49 262.3 0 0.26% g5 784.0 2 0 4 c 800.00 2.04% d4 293.6 6 54 5a 296.3 0 0.90% a5 880.0 1 8 3 2 888.89 1.01% e4 329.6 2 49 5b 326.5 3 -0.94% b5 987.7 1 6 4 a 1000.00 1.24% f4 349.2 2 46 5e 347.8 3 -0.40% c6 1046. 5 15 1 5 1066. 67 1.93%
sh6511/SH6511B 10/22 ver 2.2 music tabl e2: follow i ng is the mu sic s c al e refer e n c e ta ble for cha nne l 1 (or ch ann el 2) und er ac tual c l o ck= 16kh z . note ideal freq. n lsfr (c 1.6~c 1 .0) (c 2.14~c 2 . 8 ) r eal freq. error % n ote ideal freq. n lsfr (c 1.6~c 1 .0) (c 2.14~c 2 . 8 ) r eal freq. error % c2 65.41 122 20 65.57 0.26% g3 195.9 9 41 58 195.1 2 -0.44% d2 73.41 109 51 73.39 -0.03% a3 220.0 0 36 1a 222.2 2 1.01% e2 82.41 97 45 82.47 0.08% b3 246.9 4 32 25 250.0 0 1.24% f2 87.31 92 33 86.96 -0.40% c4 261.6 2 31 4b 258.0 6 -1.36% g2 98.00 82 27 97.56 -0.44% d4 293.6 6 27 3b 296.3 0 0.90% a2 110.0 0 73 21 109.5 9 -0.37% e4 329.6 2 24 5c 333.3 3 1.13% b2 123.4 7 65 44 123.0 8 -0.32% f4 349.2 2 23 39 347.8 3 -0.40% c3 130.8 1 61 49 131.1 5 0.26% g4 391.9 9 20 4c 400.0 0 2.04% d3 146.8 3 54 5a 148.1 5 0.90% a4 439.9 9 18 32 444.4 4 1.01% e3 164.8 1 49 5b 163.2 7 -0.94% b4 493.8 7 16 4a 500.0 0 1.24% f3 174.6 1 46 5e 173.9 1 -0.40% c5 523.2 4 15 15 533.3 3 1.93% music tabl e3: follow i ng is the mu sic s c al e refer e n c e ta ble for cha nne l 1 (or ch ann el 2) und er ac tual c l o ck= 8kh z . note ideal freq. n lsfr (c 1.6~c 1 .0) (c 2.14~c 2 . 8 ) r eal freq. error % n ote ideal freq. n lsfr (c 1.6~c 1 .0) (c 2.14~c 2 . 8 ) r eal freq. error % c1 32.70 122 20 32.79 0.26% g2 98.00 41 58 97.56 -0.44% d1 36.71 109 51 36.70 -0.03% a2 110.0 0 36 1a 111.1 1 1.01% e1 41.20 97 45 41.24 0.08% b2 123.4 7 32 25 125.0 0 1.24% f1 43.65 92 33 43.48 -0.40% c3 130.8 1 31 4b 129.0 3 -1.36% g1 49.00 82 27 48.78 -0.44% d3 146.8 3 27 3b 148.1 5 0.90% a1 55.00 73 21 54.79 -0.37% e3 164.8 1 24 5c 166.6 7 1.13% b1 61.73 65 44 61.54 -0.32% f3 174.6 1 23 39 173.9 1 -0.40% c2 65.41 61 49 65.57 0.26% g3 195.9 9 20 4c 200.0 0 2.04% d2 73.41 54 5a 74.07 0.90% a3 220.0 0 18 32 222.2 2 1.01% e2 82.41 49 5b 81.63 -0.94% b3 246.9 4 16 4a 250.0 0 1.24% f2 87.31 46 5e 86.96 -0.40% c4 261.6 2 15 15 266.6 7 1.93% music tabl e4: follow i ng is the mu sic s c al e refer e n c e ta ble for cha nne l 1 (or ch ann el 2) und er ac tual c l o ck= 4kh z . note ideal freq. n lsfr (c 1.6~c 1 .0) (c 2.14~c 2 . 8 ) r eal freq. error % n ote ideal freq. n lsfr (c 1.6~c 1 .0) (c 2.14~c 2 . 8 ) r eal freq. error % c0 16.35 122 20 16.39 0.26% g1 49.00 41 58 48.78 -0.44% d0 18.35 109 51 18.35 -0.03% a1 55.00 36 1a 55.56 1.01% e0 20.60 97 45 20.62 0.08% b1 61.73 32 25 62.50 1.24% f0 21.83 92 33 21.74 -0.40% c2 65.41 31 4b 64.52 -1.36% g0 24.50 82 27 24.39 -0.44% d2 73.41 27 3b 74.07 0.90% a0 27.50 73 21 27.40 -0.37% e2 82.41 24 5c 83.33 1.13% b0 30.87 65 44 30.77 -0.32% f2 87.31 23 39 86.96 -0.40% c1 32.70 61 49 32.79 0.26% g2 98.00 20 4c 100.0 0 2.04% d1 36.71 54 5a 37.04 0.90% a2 110.0 0 18 32 111.1 1 1.01% e1 41.20 49 5b 40.82 -0.94% b2 123.4 7 16 4a 125.0 0 1.24% f1 43.65 46 5e 43.48 -0.40% c3 130.8 1 15 15 133.3 3 1.93%
sh6511/SH6511B 11/22 ver 2.2 7. lc d t he lc d has 8 c om m on sig nal pad s, a co ntro ller, a lc d v olta ge gen erator , an d 40 se gme nt dr iv er pa ds. t he con t rol l er con s is ts of di sp lay dat a r a m and a duty g ener ator. lc d i s 1/8 duty , a nd 1 / 4 b i as . t he lc d da ta r a m is a d ual port r a m that auto m ati c a lly tran sfer s da ta t o se gm ent. t he lc d can be turne d off w i th the inter nal lc d o ff reg i st er. (a) lc d ra m area c onfigur atio n: a ddre s s bit3 bit2 bit1 bit0 $300 seg 1 seg 1 seg 1 seg 1 $301 seg 2 seg 2 seg 2 seg 2 $302 seg 3 seg 3 seg 3 seg 3 $303 seg 4 seg 4 seg 4 seg 4 $304 seg 5 seg 5 seg 5 seg 5 $305 seg 6 seg 6 seg 6 seg 6 $306 seg 7 seg 7 seg 7 seg 7 $307 seg 8 seg 8 seg 8 seg 8 $308 seg 9 seg 9 seg 9 seg 9 $309 seg 10 seg 10 seg 10 seg 10 $30a seg 11 seg 11 seg 11 seg 11 $30b seg 12 seg 12 seg 12 seg 12 $30c seg 13 seg 13 seg 13 seg 13 $30d seg 14 seg 14 seg 14 seg 14 $30e seg 15 seg 15 seg 15 seg 15 $30f seg 16 seg 16 seg 16 seg 16 $310 seg 17 seg 17 seg 17 seg 17 $311 seg 18 seg 18 seg 18 seg 18 $312 seg 19 seg 19 seg 19 seg 19 $313 seg 20 seg 20 seg 20 seg 20 $314 seg 21 seg 21 seg 21 seg 21 $315 seg 22 seg 22 seg 22 seg 22 $316 seg 23 seg 23 seg 23 seg 23 $317 seg 24 seg 24 seg 24 seg 24 $318 seg 25 seg 25 seg 25 seg 25 $319 seg 26 seg 26 seg 26 seg 26 $31a seg 27 seg 27 seg 27 seg 27 $31b seg 28 seg 28 seg 28 seg 28 $31c seg 29 seg 29 seg 29 seg 29 $31d seg 30 seg 30 seg 30 seg 30 $31e seg 31 seg 31 seg 31 seg 31 $31f seg 32 seg 32 seg 32 seg 32 $320 seg 33 seg 33 seg 33 seg 33 $321 seg 34 seg 34 seg 34 seg 34 $322 seg 35 seg 35 seg 35 seg 35 $323 seg 36 seg 36 seg 36 seg 36 $324 seg 37 seg 37 seg 37 seg 37 $325 seg 38 seg 38 seg 38 seg 38 $326 seg 39 seg 39 seg 39 seg 39 $327 seg 40 seg 40 seg 40 seg 40 dut y com 4 com 3 com 2 com 1
sh6511/SH6511B 12/22 ver 2.2 lc d r a m area c onfi gurat ion ( c o n tin ued): a ddress bit 3 b it 2 b it 1 b it 0 $328 seg 1 seg 1 seg 1 seg1 $329 seg 2 seg 2 seg 2 seg2 $32a seg 3 seg 3 seg 3 seg3 $32b seg 4 seg 4 seg 4 seg4 $32c seg 5 seg 5 seg 5 seg5 $32d seg 6 seg 6 seg 6 seg6 $32e seg 7 seg 7 seg 7 seg7 $32f seg 8 seg 8 seg 8 seg8 $330 seg 9 seg 9 seg 9 seg9 $331 seg 10 seg 10 seg 10 seg10 $332 seg 11 seg 11 seg 11 seg11 $333 seg 12 seg 12 seg 12 seg12 $334 seg 13 seg 13 seg 13 seg13 $335 seg 14 seg 14 seg 14 seg14 $336 seg 15 seg 15 seg 15 seg15 $337 seg 16 seg 16 seg 16 seg16 $338 seg 17 seg 17 seg 17 seg17 $339 seg 18 seg 18 seg 18 seg18 $33a seg 19 seg 19 seg 19 seg19 $33b seg 20 seg 20 seg 20 seg20 $33c seg 21 seg 21 seg 21 seg21 $33d seg 22 seg 22 seg 22 seg22 $33e seg 23 seg 23 seg 23 seg23 $33f seg 24 seg 24 seg 24 seg24 $340 seg 25 seg 25 seg 25 seg25 $341 seg 26 seg 26 seg 26 seg26 $342 seg 27 seg 27 seg 27 seg27 $343 seg 28 seg 28 seg 28 seg28 $344 seg 29 seg 29 seg 29 seg29 $345 seg 30 seg 30 seg 30 seg30 $346 seg 31 seg 31 seg 31 seg31 $347 seg 32 seg 32 seg 32 seg32 $348 seg 33 seg 33 seg 33 seg33 $349 seg 34 seg 34 seg 34 seg34 $34a seg 35 seg 35 seg 35 seg35 $34b seg 36 seg 36 seg 36 seg36 $34c seg 37 seg 37 seg 37 seg37 $34d seg 38 seg 38 seg 38 seg38 $34e seg 39 seg 39 seg 39 seg39 $34f seg 40 seg 40 seg 40 seg40 dut y com 8 com 7 com 6 com5
sh6511/SH6511B 13/22 ver 2.2 (b) lcd voltage generator lc d v o ltage s v1, v2, v3 are obta i ne d u s ing res i st or d i v i der ne tw ork. t he lc d c an b e tur ned off by w i th th e lc d o ff re gis t er. (c) lcd wav e form t he output w a v e form of 1/8 d u ty and 1/4 bia s i s show n bel ow . v1 v2 v3 gnd v1 v2 v3 gnd v1 v2 v3 gnd v dd v1 v2 v3 gnd seg com3 com2 com1 v dd v dd v dd
sh6511/SH6511B 14/22 ver 2.2 8. interrupt tw o interrupt so urce s ar e av ail a b l e o n the sh 651 1/sh 65 11b: - t i m e r0 i n terru pt (t m r 0) - port fa lli ng e dge dete c ti on i n terr upt ( pb ) (a) interr upt co ntro l bit s an d int e rrup t serv ic e: - i nterru pt c ontro l fl ags are ma pped on $00 t h rou gh $ 01 o f th e sy st em r egi ster. t hey can b e ac c e s s ed or te sted by the progra m . t hes e fl ags are cle a red to 0 at i n it ial i z a tio n . bit 3 b it 2 b it 1 b it 0 r emarks $00 - iet0 - iep interrupt enable flags $01 - irqt0 - irqp interrupt request flags - i nterru pt req u e s t be gin s w hen ir q x is set t o 1 and iex is 1 . at th is tim e , i n terr upt w ill a c tiv a te an d v e ct or ad dres s w ill com m en ce from the prior i ty pla c o rre spon din g to the interr upt sou r ce. w h e n an int e rrupt occ u r s , th e pc an d c y flags w ill be s a v ed in st ac k me mory a nd j u mp to an i n terru pt s e rv ice v e ctor addr es s. aft e r in terru pt o ccur s , all inter r upt ena b le flag s (iex ) are automa t ic ally re set to 0 , so any i n terru pt i s d i sa ble d . t he ir q x , w h ich ca us ed i n terru pt, mu st be res e t by softw are in the inte rrupt serv i c e ro utin e. w h en iex is set t o 1 a gai n, sh 65 11/sh 6 511b can serv i c e mult i-lev e l in terru pts. (b) vect or addr es s a nd in terrup t prior i ty priority interrupt source 1 (most) reset 2 reserved 3tmr0 4 reserved 5 (least) pb 9. s y stem c l ock an d o scill ation c i r c uit t he sy stem cl oc k ge nerat or pro d u c es cl oc k pu ls es sup p li ed to the c p u and on-ch i p per iph e ral s . - i nstru c ti on cy cle tim e 2 s for 2 m h z clock 10. ha lt or sto p - a fter ex ecutio n of h a lt , sh 6511/sh 6 511b w ill enter h a lt . in h a lt , the c p u w ill stop oper ati ng, b u t th e p e riph eral cir c u i t (timer) w ill ope rate. - a fter ex ecutio n of st o p , sh 651 1/sh 651 1b w ill en ter st o p . in st o p , the ent ire chi p (i ncl udi ng o s c ill ator) w ill sto p operat ing, and the lc d aut oma t i c al ly pow ers-off. in h a lt , sh 6511/sh 6 511b w ill w a ke up if a n in terrup t o ccurs . in st o p , sh 6511/sh 65 11b w ill w a ke u p if port inte rrupt oc cur s . 11. war m -up ti mer t he w arm-up tim er e lim inat es a n init ial os cil l at ion ins t ab ility i n th e fo llow i ng tw o ca se s: 1) power-on reset 2) w a k e - up fr om st o p . t he w a rm-up tim e in terv al is 32 c l o ck cy cle s .
sh6511/SH6511B 15/22 ver 2.2 12. s y stem r eset - hardw a re res e t in put - w a rm - up ti m e r for p o w e r-on res e t (a) init ial state h a r d w a r e a fter pow e r - on r eset program counter $000 cy undefined data memory undefined system register undefined ac undefined timer counter undefined timer load register undefined interrupt enable flags 0 interrupt request flags 0 dph, dpm, dpl undefined tbr undefined lcd driver output active port a $0 port b $f bank bit 2, 1, 0 $0
sh6511/SH6511B 16/22 ver 2.2 13. in st ru ct io n set all in stru cti o n s are one cy cl e an d on e w o rd in stru ctio ns. t he c h a r act e ri sti c i s m e mory -or i ente d o p erat ion . arithm eti c an d lo gi cal in stru ctio n a ccu mul a tor t y pe mnemo n ic instruction code function flag chan ge ad c x ( ,b) 00000 0b bb x x x x x x x ac m x + ac + cy cy ad c m x ( ,b) 00000 1b bb x x x x x x x ac, m x m x + ac + c y cy ad d x ( ,b) 00001 0b bb x x x x x x x ac mx + a c cy ad d m x ( ,b) 00001 1b bb x x x x x x x ac, m x mx + a c cy sbc x ( ,b) 00010 0b bb x x x x x x x ac m x + -ac + cy cy sbc m x ( ,b) 00010 1b bb x x x x x x x ac, m x m x + -ac + cy cy su b x ( ,b) 00011 0b bb x x x x x x x ac m x + -ac + 1 cy su b m x ( ,b) 00011 1b bb x x x x x x x ac, m x m x + -ac +1 cy eo r x ( ,b) 00100 0b bb x x x x x x x ac mx ac eo r m x ( ,b) 00100 1b bb x x x x x x x ac,mx mx ac o r x ( ,b) 00101 0b bb x x x x x x x ac mx | ac o r m x ( ,b) 00101 1b bb x x x x x x x ac,mx mx | ac an d x ( ,b) 00110 0b bb x x x x x x x ac mx & ac an d m x ( ,b) 00110 1b bb x x x x x x x ac,mx mx & ac imme dia t e t y pe mnemo n ic instruction code function flag change ad i x , i 01000 ii ii x x x x x x x ac mx + i cy ad i m x , i 01001 ii ii x x x x x x x ac, m x mx + i cy sbi x , i 01010 ii ii x x x x x x x ac m x + -i +1 cy sbim x , i 01011 ii ii x x x x x x x ac, m x m x + -i + 1 cy eo r i m x , i 01100 ii ii x x x x x x x ac,mx mx i o r i m x , i 01101 ii ii x x x x x x x ac,mx mx | i an d i m x , i 01110 ii ii x x x x x x x ac,mx mx & i * in the as se mbl e r asm 66 v1.0, eo r i m mnemon ic is eo r i. h o w e v e r, eo r i ha s the sa me o p er atio n i d ent i ca l w i th eo r i m . same f o r th e o r im w i th respec t t o o r i, and andim w i th respe c t t o andi. d e ci mal a d ju stm ent mnemonic instruction code function flag change daa x 11001 0110 xxx xxxx ac; mx decimal adjustment for add. cy das x 11001 1010 xxx xxxx ac; mx decimal adjustment for sub. cy
sh6511/SH6511B 17/22 ver 2.2 t r ansfer in stru cti o n mnemo n ic instruction code function flag chan ge ld a x ( ,b) 00111 0b bb x x x x x x x ac mx st a x ( ,b) 00111 1b bb x x x x x x x m x ac ld i x , i 01111 ii ii x x x x x x x ac, m x i control ins t ruc t ion mnemonic instruction code function flag change baz x 10010 xxxx xxx xxxx pc x if ac=0 bc x 10011 xxxx xxx xxxx pc x if cy=1 ba0 x 10100 xxxx xxx xxxx pc x if ac(0)=1 ba1 x 10101 xxxx xxx xxxx pc x if ac(1)=1 ba2 x 10110 xxxx xxx xxxx pc x if ac(2)=1 ba3 x 10111 xxxx xxx xxxx pc x if ac(3)=1 c a ll x 11000 xxxx xx x xxx x st cy ; pc +1 pc x(not including p) rtnw h;l 11010 000h hhh llll pc st; tbr hhhh; ac llll rtni 11010 10 00 0 00 0 000 cy ;pc st cy halt 11011 00 00 0 00 0 000 stop 11011 10 00 0 00 0 000 jm p x 1110p xxxx xx x xxx x pc x(include p) t j m p 11110 11 11 1 11 1 111 pc (pc11-pc8) (tbr) (a) n o p 11111 11 11 1 11 1 111 no operation w her e , pc program co unter i immediate data ac accu mul a tor logical exclusive or -ac c ompl eme n t of ac cu mul a tor | logical or c y c a rry flag & logical and m x d a ta m e mory bbb ram bank=000 p rom page =0 st stack t br table branch register
sh6511/SH6511B 18/22 ver 2.2 a b so lu t e m aximu m rat i n g s * d c supply volt age . . . . . . . . . . . . . . . . . . . . -0.3v t o +7v input v o lta ge . . . . . . . . . . . . . . . . . . . .-0. 3v to v dd +0.3v o peratin g am bie n t t e mper atur e . . . . . . . .-1 0 c to + 6 0 c storage t e m pera t ure . . . . . . . . . . . . . . . -55 c to +1 25 c * c omments stress es abov e t hos e l i st ed u nder "abs olu t e m a x i mum r a ting s" may c aus e per man e nt da mage to t h is dev i ce. t hese are stre ss rati ng s on ly . fun c tio nal oper ati o n of thi s dev ice at th es e or a n y other co ndit i on s a b ov e th ose indi cat ed i n th e op erati ona l s ect ion s of thi s s pec ifi c at ion is not i m pl ied or i n ten ded. ex posure to the abs olu t e max i mum rating co ndit i on s fo r ex tended p eri ods may af fect dev i c e relia bil i ty . dc el ect ri cal ch ara c t e ri st ics (v dd = 3.0v, g n d = 0v, t a = 2 5 c, f osc = 2 m h z , unless o t herw ise sp ecif ied ) s y mbol parameter m in. t y p . m ax. unit conditions v dd o peratin g vol t age 2.4 3.0 3.4 v i op o peratin g c u rre nt 0.1 0 .19 m a v dd = 3.0v, no load i sb standby c u rre nt 0.7 1 .2 a v dd = 3.0v, o sc stop, all outputs unloaded i i input c u rrent 6 3 5 a v dd = 3.0v v(input) = 3. 0v v ih input h i gh v o lta g e v dd -0.5 v dd +0.3 v v il input low voltag e - 0.3 g n d + 0.5 v i ol o u tput l o w d r iv e c u rrent 1.8 m a po r t a and po rtb, v ol = 0.5v i oh o u tput h i g h d r iv e c u rr ent 250 a port a, v ol = v dd -0.5v i oh i ol ao u t ou tput c u rre nt 1.2 1.2 ma ma v ou t = v dd -0. 6 v v ou t = 0.5v r pu pull-u p r e s i st anc e 20 100 k ? port b
sh6511/SH6511B 19/22 ver 2.2 a p pli c a t ion ci r c uit (for re fe re nc e onl y ) : ap 1 : seg6 seg5 seg4 seg3 seg2 seg1 s e g 2 9 seg30 seg31 seg32 seg33 seg34 seg35 seg36 seg37 seg38 seg39 seg40 p a 3 lcd panel ( 40 x 8 ) 1/8 duty 1/4 bias um5003dh -1a/1c trg1 trg2 trg3 trg4 osc r5 300k aud 1 r3 1.2k gnd 3.0v 0.47m f c2 pb0 gnd osci aout reset r6 120k 10k r2 reset 1 r1 6.2k 8050 q1 speaker sp1 sh6511/SH6511B + v dd v dd v dd p a 2 p a 1 p a 0 c o m 1 c o m 2 c o m 3 c o m 4 c o m 5 c o m 6 c o m 7 c o m 8 v dd s e g 2 8 s e g 2 7 s e g 2 6 s e g 2 5 s e g 2 4 s e g 2 3 s e g 2 2 s e g 2 1 s e g 2 0 s e g 1 9 s e g 1 8 s e g 1 7 s e g 1 6 s e g 1 5 s e g 1 4 s e g 1 3 s e g 1 2 s e g 1 1 s e g 1 0 s e g 9 s e g 8 s e g 7 pb1 pb2 pb3 v dd 1.5~3.0v 10 11 1 2 3 7 pb3 2 sec 31.2m s 32768hz x'tal um3252a/62a
sh6511/SH6511B 20/22 ver 2.2 ap 2 : seg6 seg5 seg4 seg3 seg2 seg1 s e g 2 9 seg30 seg31 seg32 seg33 seg34 seg35 seg36 seg37 seg38 seg39 seg40 p a 3 lcd panel ( 40 x 8 ) 1/8 duty 1/4 bias pb0 gnd osci aout reset r6 120k reset sh6511/SH6511B v dd p a 2 p a 1 p a 0 c o m 1 c o m 2 c o m 3 c o m 4 c o m 5 c o m 6 c o m 7 c o m 8 v dd s e g 2 8 s e g 2 7 s e g 2 6 s e g 2 5 s e g 2 4 s e g 2 3 s e g 2 2 s e g 2 1 s e g 2 0 s e g 1 9 s e g 1 8 s e g 1 7 s e g 1 6 s e g 1 5 s e g 1 4 s e g 1 3 s e g 1 2 s e g 1 1 s e g 1 0 s e g 9 s e g 8 s e g 7 pb1 pb2 pb3 v dd 1.5~3.0v 10 11 1 2 3 7 pb3 2 sec 31.2m s 32768hz x'tal um3252a buzzer 1n4148
sh6511/SH6511B 21/22 ver 2.2 bonding dia g r a m 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 seg23 seg21 seg22 seg24 seg25 seg26 seg27 seg28 seg29 seg30 seg31 seg32 seg33 seg34 seg36 seg35 sh6511/ SH6511B 27 26 25 24 23 22 18 17 16 com4 com5 com6 com7 com8 seg1 21 20 19 seg2 com3 seg7 6 5 4 3 2 11 2 11 10 9 8 7 15 14 13 31 30 29 28 46 45 44 43 40 37 36 35 34 33 32 38 39 41 42 48 47 seg38 seg37 seg6 seg5 seg4 seg3 com2 com1 pb3 pb2 pb1 s e g 3 9 s e g 4 0 t e s t r e s e t a o u t o p 0 o s c i o p 1 p a 0 p a 1 p a 2 p a 3 p b 0 g n d v d d s e g 9 s e g 8 s e g 1 0 s e g 1 1 s e s 1 2 s e g 1 3 s e g 1 4 s e g 1 5 s e g 1 6 s e g 1 7 s e g 1 8 s e g 1 9 s e g 2 0 1790 m 2130 m (0, 0) * substr ate conn ect to g n d unit: m pad no. d esignati on x y 1 seg 21 -770 935 2 seg 20 -660 935 3 seg 19 -550 935 4 seg 18 -440 935 5 seg 17 -330 935 6 seg 16 -220 935 7 seg 15 -110 935 8 seg14 0 935 9 seg 13 110 935 10 seg 12 220 935 11 seg 11 330 935 12 seg 10 440 935 13 seg 9 550 935 14 seg 8 660 935 15 seg 7 770 935 16 seg 6 770 825 17 seg 5 770 715 18 seg 4 770 605 19 seg 3 770 495 20 seg 2 770 385 21 seg 1 770 275 22 c o m 8 770 165 23 c o m 7 770 55 24 c o m 6 770 -55 25 c o m 5 770 -165 26 c o m 4 770 -275 27 c o m 3 770 -385 28 c o m 2 770 -495 29 c o m 1 770 -605 30 pb3 770 -715 31 pb2 770 -825 32 pb1 770 -935 pad no. d esignati on x y 33 pb0 660 -935 34 pa3 550 -935 35 pa2 440 -935 36 pa1 330 -935 37 pa0 220 -935 38 o p 1 110 -935 39 v dd 110 -840 40 o s c i 0 - 935 41 o p 0 - 110 -935 42 g n d - 110 -840 43 ao u t -220 -935 44 reset -330 -935 45 test -440 -935 46 seg 40 -550 -935 47 seg 39 -660 -935 48 seg 38 -770 -935 49 seg 37 -770 -825 50 seg 36 -770 -715 51 seg 35 -770 -605 52 seg 34 -770 -495 53 seg 33 -770 -385 54 seg 32 -770 -275 55 seg 31 -770 -165 56 seg 30 -770 -55 57 seg 29 -770 55 58 seg 28 -770 165 59 seg 27 -770 275 60 seg 26 -770 385 61 seg 25 -770 495 62 seg 24 -770 605 63 seg 23 -770 715 64 seg 22 -770 825
sh6511/SH6511B 22/22 ver 2.2 or de r i ng infor m a t ion par t n o . p ackag e sh6511/SH6511Bh-xx xxx chip form p r ogra mming note (for referen c e o n ly ): z e x ecute h a lt in stru cti on fre que ntly . z t u rn off psg w hen it i s n o t u s ed. z r educ e the freq uen cy of sy s t em cl oc k by en larg ing the v a lue o f th e ex ternal re si stor that con n e c ts to th e o s c i pi n. but the low e r freque ncy i s , th e po orer lc d perfor m a n ce is. it i s re com m ende d th at lc d fr ame freq uen cy mu st ov er 2 6 h z , that is, sy stem cl oc k ov er 1 . 625 m h z . h o w ev er, lc d panel o perat ing freq uen cy sho uld me et th e lc d fra m e frequ en c y of sh6511/SH6511B. p i n opti on i n th e pro g ram for diff erent sy ste m clo ck fr equ ency mig h t be the goo d c h oi ce f o r th e fir s t code that prov id es an a l tern ativ e f o r di ffere nt lc d p ane l per form an ce. z since the v a r i ati on o f sy st em cl oc k i s aff e cte d by th e v a lu e of t he ex ternal res i st or th at c onne ct s to o s c i p i n, it i s sugg est ed t o us e th e re sist or w i th 3 % pre c i s io n. z t o get real ti me clo ck, one ana log cl oc k c hip, u m 3252a/62a, i s u s e d to gener ate a 2h z pu lse that is co nne cted to t he port b of sh 651 1/sh 65 11b. z t he norma l op erat ing curre nt of sh 651 1/sh 65 11b for f osc = 2 m h z is about 100 ua~80 u a. if 8 0 mah r batt e ry is use d , 1000- hour ( ~ 42 day s) l i fet i me ca n be rea c he d ea si ly .

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